The present invention relates to semiconductor design technologies; and, more particularly, to a control signal generator for a bit line sense amplifier driver for use in the semiconductor memory device.
In recent semiconductor memory devices, a power supply voltage is being increasingly reduced as a line width and a cell size become continuously scaled down. Thus, a need has existed for a design technology to meet the performance required in the low voltage environment.
Meanwhile, most semiconductor memory devices incorporate an internal voltage generation circuit for taking an external voltage (power supply voltage) and generating an internal voltage within a chip to supply voltages needed in circuits inside the chip. Among them, in memory devices using a bit line sense amplifier (BLSA) such as DRAM, a core voltage VCORE has been used for sensing cell data.
But, when only the core voltage VCORE is utilized in the DRAM which is under a trend that an operating voltage is being lowered, it is difficult to amplify a large amount of cell data for a short time.
To solve the above problem, a BLSA over driving method has been employed, in which a pull-up power line of the BLSA is driven by a voltage (generally, power supply voltage VDD) higher than the core voltage VCORE for a certain time during an initial operation (immediately after charge sharing between a memory cell and a bit line) of the BLSA.
FIG. 1 is a circuit diagram illustrating a conventional BLSA driver.
Referring to FIG. 1, the BLSA driver is provided with a normal driver N2 for driving a pull-up power line RTO of the BLSA with a normal driving voltage VCORE, an over driver N1 for driving the pull-up power line RTO of the BLSA with an over driving voltage VDD, and a pull-down driver N3 for driving a pull-down power line SB of the BLSA with a pull-down driving voltage VSS. In addition, the BLSA driver is further provided with a power line precharge part 11 for precharging the power lines RTO and SB of the BLSA.
Briefly explaining an operation, when data stored in a memory cell is carried on bit lines BL/BLB, there occurs a potential difference (A interval).
The BLSA is operated to amplify the potential difference. That is, the BLSA driver first drives the pull-up power line RTO of the BLSA with the over driving voltage VDD (B interval) to thus improve the sensing capability of the BLSA. At this time, the over driver N1 is driven by taking an over driving signal SAP1 via its gate. This over driving interval B is a fixed interval which is set by considering the sensing time and sensing efficiency.
Next, the over driving signal SAP1 is inactivated and the normal driving signal SAP2 is activated, so that the pull-up power line RTO of the BLSA is driven by the normal driving voltage VCORE (C interval).
When the pull-up power line RTO of the BLSA is driven by the over driving voltage VDD or the normal driving voltage VCORE, the pull-down power line SB should also be driven by the pull-down driving voltage VSS.
By the operation of the BLSA driver, the BLSA is operated, wherein a variation of the voltage level of the bit lines BL/BLB by the operation of the BLSA will be shown below.
FIG. 2 is a diagram describing a variation of a voltage level on bit lines according to the operation of the BLSA.
Referring to FIG. 2, the bit lines BL/BLB are driven by a precharge voltage VCORE/2 by a precharge operation of a semiconductor memory device (D interval).
Thereafter, the data is outputted from the memory cell, and a potential difference exists between the bit lines BL/BLB (A interval) and is further amplified by the over driving operation of the BLSA (B interval). Subsequently, the data is maintained by a normal driving operation (C operation) after securing the sensing capability as desired.
After the data is carried on a data transfer line, the bit lines BL/BLB are driven by the precharge voltage VCORE/2.
Here, the over driving operation refers to an operation in which the pull-up power line of the BLSA is driven by the over driving voltage VDD, as set forth above.
Further, the over driving voltage VDD is a voltage applied from outside, and its level is varied as the environment.
Under the above circumstance, although the over driving operation (B interval) is ended and converted into the normal driving operation (C interval), the voltage level of the bit lines (BL/BLB) does not become the core voltage VCORE but has a voltage level which is greater than the core voltage VCORE.
FIG. 3 is a diagram describing the bit lines (BL/BLB) with a voltage level increased by an excessive over driving operation.
Referring to FIG. 3, the bit lines BL/BLB are driven by an excessive over driving voltage VDD+β during the over driving operation and maintain a higher voltage level than the core voltage VCORE, even during the normal driving operation.
Further, after the sensing operation has been completed, the bit lines BL/BLB are also driven by a higher voltage level VCORE/2+Δ than the precharge voltage VCORE/2.
This acts as a factor that obstructs not only the operation of the semiconductor memory device but also the security of the semiconductor memory device with a low power.
Thus, in order to drop the increased voltage level by the excessive over driving operation as above, the semiconductor memory device is further provided with a core voltage discharge device. However, this discharge operation causes an unnecessary current consumption.
On the contrary, in case where the level of the over driving voltage VDD is low, there may occur a problem in which the over driving operation is ended before the bit lines BL/BLB reach the core voltage VCORE by the fixed over driving interval (see FIG. 4). This becomes a reason that reduces the sensing capability of the BLSA.